Challagundla, DhandeepBezzam, IgnatiusIslam, Riadul2025-04-232025-04-232024-11-25Challagundla, Dhandeep, Ignatius Bezzam, and Riadul Islam. “ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33, no. 1 (January 2025): 179–92. https://doi.org/10.1109/TVLSI.2024.3502359.Challagundla, Dhandeep, Ignatius Bezzam, and Riadul Islam. “ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33, no. 1 (January 2025): 179–92. https://doi.org/10.1109/TVLSI.2024.3502359.https://doi.org/10.1109/TVLSI.2024.3502359http://hdl.handle.net/11603/38019While general-purpose computing follows von Neumann’s architecture, the data movement between memory and processor elements dictates the processor’s performance. The evolving compute-in-memory (CiM) paradigm tackles this issue by facilitating simultaneous processing and storage within static random-access memory (SRAM) elements. Numerous design decisions taken at different levels of hierarchy affect the figures of merit (FoMs) of SRAM, such as power, performance, area, and yield. The absence of a rapid assessment mechanism for the impact of changes at different hierarchy levels on global FoMs poses a challenge to accurately evaluating innovative SRAM designs. This article presents an automation tool designed to optimize the energy and latency of SRAM designs incorporating diverse implementation strategies for executing logic operations within the SRAM. The tool structure allows easy comparison across different array topologies and various design strategies to result in energy-efficient implementations. Our study involves a comprehensive comparison of over 6900+ distinct design implementation strategies for École Polytechnique Fédérale de Lausanne (EPFL) combinational benchmark circuits on the energy-recycling resonant CiM (rCiM) architecture designed using Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology. When provided with a combinational circuit, the tool aims to generate an energy-efficient implementation strategy tailored to the specified input memory and latency constraints. The tool reduces 80.9% of energy consumption on average across all benchmarks while using the six-topology implementation compared with the baseline implementation of single-macro topology by considering the parallel processing capability of rCiM cache size ranging from 4 to 192 kB.14 pagesen-US© 2025 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Recyclingresonant energy-recyclingOptimizationIn-memory computingmemory bottleneckCompute-in-memory (CiM)Discharges (electric)InductorsUMBC Cybersecurity InstituteLogiclogic synthesisComputer architectureRandom access memorystatic random-access memory (SRAM)MicroprocessorsEnergy efficiencyText