Negative Capacitance Clock Distribution
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Date
2018-09-27
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Citation of Original Publication
R. Islam, "Negative Capacitance Clock Distribution," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 1, pp. 547-553, 1 Jan.-March 2021, doi: 10.1109/TETC.2018.2872000.
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© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
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Abstract
In this paper, we investigate the ever-increasing power issue that is poised to jeopardize the performance and robustness of future low-power microprocessor design. We have observed a tremendous amount of research in low-power clock network design to bolster energy-efficient computing, without, however, any substantial improvement in overall microprocessor clock power and performance. In this work, we used the emerging ferroelectric negative capacitance field-effect transistor (NCFET) to reduce clock network effective capacitance and active elements, which enables low-power clocking. According to accurate HSPICE simulation, the proposed NCFET-based clocking can save up to 70 and 73 percent average power compared to the industry standard clocking schemes on industrial ISPD 2009 and ISPD 2010 benchmarks, respectively. In addition, the proposed methodology uses up to 20 percent fewer clock buffers compared to the existing synthesized clocking scheme and exhibits 49 percent lower crosstalk-induced delay variation compared to the traditional CMOS-based design.