Power and Skew Reduction Using Resonance Energy Recycling in FinFET based Wideband Clock Networks

Abstract

Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. Besides, the rising demand of high-performance microprocessors increases the circuit complexity and the rate of data transfer resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series LC resonance. Moreover, this work also proposes wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing theskew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks, and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to a conventional primary-secondary flip-flop-based clock network.