Resonant Energy Recycling SRAM Architecture

dc.contributor.authorIslam, Riadul
dc.contributor.authorSaha, Biprangshu
dc.contributor.authorBezzam, Ignatius
dc.date.accessioned2021-04-14T16:23:00Z
dc.date.available2021-04-14T16:23:00Z
dc.description.abstractAlthough we may be at the end of Moore’s law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.en_US
dc.description.urihttps://ieeexplore.ieee.org/document/9215044en_US
dc.format.extent5 pagesen_US
dc.genrejournal articles preprintsen_US
dc.identifierdoi:10.13016/m2unq9-xlij
dc.identifier.citationRiadul Islam, Biprangshu Saha and Ignatius Bezzam, Resonant Energy Recycling SRAM Architecture, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 68, Issue: 4, DOI:10.1109/TCSII.2020.3029203en_US
dc.identifier.urihttps://doi.org/10.1109/TCSII.2020.3029203
dc.identifier.urihttp://hdl.handle.net/11603/21330
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.isAvailableAtThe University of Maryland, Baltimore County (UMBC)
dc.relation.ispartofUMBC Computer Science and Electrical Engineering Department Collection
dc.relation.ispartofUMBC Faculty Collection
dc.rightsThis item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author.
dc.titleResonant Energy Recycling SRAM Architectureen_US
dc.typeTexten_US

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