High-Speed On-Chip signaling: Voltage or Current-Mode?
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Date
2018-10-22
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Citation of Original Publication
Riadul Islam (2018) High-Speed On-Chip signaling: Voltage or Current-Mode?, IETE Journal of Research, DOI: 10.1080/03772063.2018.1534618
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This item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author.
This is an Accepted Manuscript of an article published by Taylor & Francis in IETE Journal of Research on 22 Oct 2018, available online: http://www.tandfonline.com10.1080/03772063.2018.1534618
This is an Accepted Manuscript of an article published by Taylor & Francis in IETE Journal of Research on 22 Oct 2018, available online: http://www.tandfonline.com10.1080/03772063.2018.1534618
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Abstract
In this paper, we investigate several on-chip signaling schemes. Specifically, we compare different voltage-mode (VM) and current-mode (CM) signaling schemes considering power, performance, and robustness. In addition, we propose a new CM signaling scheme that uses a simple NAND-NOR gate transmitter circuit and a current-comparator-based receiver circuit. We implemented each signaling scheme using a 45 nm CMOS technology. The extracted simulation results show that a traditional CM signaling scheme consumes 58–78% less power compared to a traditional buffered VM signaling scheme in the 1–3 GHz frequency range. Our proposed CM signaling scheme consumes up to 95% and 81% lower power compared to buffered VM and existing CM schemes, respectively. In addition, the proposed CM signaling scheme has 37–41% lower latency with similar slew-rates compared to the buffered signaling scheme.