A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations

dc.contributor.authorChallagundla, Dhandeep
dc.contributor.authorBezzam, Ignatius
dc.contributor.authorIslam, Riadul
dc.date.accessioned2024-07-26T16:35:55Z
dc.date.available2024-07-26T16:35:55Z
dc.date.issued2024-06-12
dc.descriptionGLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024, June 12 - 14, 2024
dc.description.abstractIn recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate (MAC) is considered a de facto unit operation in NNs. By leveraging the minimal data movement required and inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more efficiently. Traditional CiM architectures execute MAC operations in the analog domain, employing an Analog-to-Digital converter (ADC) to digitize the analog MAC values. However, these ADCs introduce significant increase in area and power consumption, as well as introduce non-linearities. This work proposes a resonant time-domain CiM (rTD-CiM), an ADC-less architecture that reduces the power consumption of traditional CiM architectures with ADCs. The feasibility of the proposed architecture is evaluated on an 8KB SRAM memory array using TSMC 28 nm technology. The proposed rTD-CiM architecture demonstrates a throughput of 2.36 TOPS with an energy efficiency of 28.05 TOPS/W.
dc.description.sponsorshipThis work was supported in part by the Rezonent Inc. under Grant CORP0061, National Science Foundation (NSF) award number: 2138253, and the UMBC Startup grant
dc.description.urihttps://dl.acm.org/doi/10.1145/3649476.3658773
dc.format.extent4 pages
dc.genreconference papers and proceedings
dc.identifierdoi:10.13016/m24c10-vdpb
dc.identifier.citationChallagundla, Dhandeep, Ignatius Bezzam, and Riadul Islam. “A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations.” Proceedings of the Great Lakes Symposium on VLSI 2024, GLSVLSI ’24, June 12, 2024, 268–71. https://doi.org/10.1145/3649476.3658773.
dc.identifier.urihttps://doi.org/10.1145/3649476.3658773
dc.identifier.urihttp://hdl.handle.net/11603/35148
dc.language.isoen_US
dc.publisherACM
dc.relation.isAvailableAtThe University of Maryland, Baltimore County (UMBC)
dc.relation.ispartofUMBC Faculty Collection
dc.relation.ispartofUMBC Student Collection
dc.relation.ispartofUMBC Computer Science and Electrical Engineering Department
dc.rightsCC BY 4.0 Deed ATTRIBUTION 4.0 INTERNATIONAL
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subjectStatic Random Access Memory (SRAM)
dc.subjectmultiply-accumulate (MAC)
dc.subjectconvolution neural network (CNN)
dc.subjectcompute-in-memory (CiM)
dc.subjecttime-to-digital converter (TDC).
dc.titleA Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations
dc.typeText
dcterms.creatorhttps://orcid.org/0000-0001-7491-1710
dcterms.creatorhttps://orcid.org/0000-0002-4649-3467

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