Multi-core implementation for Bare Machine Computing

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dc.contributor.advisorKarne, Ramesh K.
dc.contributor.authorChang, Hojin
dc.contributor.departmentTowson University. Department of Computer and Information Sciencesen_US
dc.date.accessioned2018-01-18T22:28:18Z
dc.date.available2018-01-18T22:28:18Z
dc.date.issued2018-01-17
dc.date.submitted2017-08
dc.description(D. Sc.) -- Towson University, 2017en_US
dc.description.abstractThis dissertation extends on-going Bare Machine Computing (BMC) research at Towson University. BMC applications run on a bare machine without any commercial operating system, kernel, or any other centralized support. This dissertation will serve as a cornerstone for future multi-core systems that run on bare machines. Multi-core processors are deployed on most desktops, laptops and other devices. Since the inception of BMC, applications were implemented on a 32-bit single core Intel architecture (x86) due to its availability and skill set in the BMC laboratory. The multi-core architecture coupled with 64-bit CPUs poses numerous challenges in implementing bare machine computing applications. This thesis lays a foundation to understand the design issues in implementing and porting existing applications to 64-bit multi-core architecture. First, the existing boot and load programs for BMC are ported to run in the new platform. This posed numerous problems due to architectural differences in 32-bit and 64-bit architectures. Second, some existing applications are ported to run on the new platform. A Web server application written for a 32-bit architecture is made to run on the new platform. This step is involved in a variety of architectural and design issues and incompatibilities among the old and new architectures. Finally, the Web server is made to run on multi-core by scheduling its threads to multiple cores. This posed a daunting challenge due to its complexity. some preliminary work in this area has been completed and the rest is left for future explorations. This dissertation developed a variety of tools and techniques that are useful for future research in BMC applications. As the current technology is moving towards multi-core CPUs, it is necessary to study this problem for BMC applications. It has been discovered that the 32-bit and 64-bit architectural differences pose major difficulties in porting existing applications to smoothly run 64-bit multi-core architecture, whether they are conventional or bare.en_US
dc.description.tableofcontentsInsight into x86_64 bare PC methodology -- Migrating a web server to a multi-core architecture -- multi-core BMC parallelization
dc.description.urihttp://library.towson.edu/digital/collection/etd/id/62690/en_US
dc.formatapplication/pdf
dc.format.extentxi, 75 pagesen_US
dc.genredissertationsen_US
dc.identifierdoi:10.13016/M29K45V22
dc.identifier.otherDSU2017Chang
dc.identifier.urihttp://hdl.handle.net/11603/7501
dc.language.isoen_USen_US
dc.relation.isAvailableAtTowson University
dc.titleMulti-core implementation for Bare Machine Computingen_US
dc.typeTexten_US

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