TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector
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Challagundla, Dhandeep, Venkata Krishna Vamsi Sundarapu, Ignatius Bezzam, and Riadul Islam. “TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector.” 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration (VLSI-SoC), October 2025, 1–5. https://doi.org/10.1109/VLSI-SoC64688.2025.11421753.
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Abstract
Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41µW at 3 GHz input frequency with a layout area of 10.42μm²