FPGA based Optical Two-way Time Transfer for Clock Correction through Dynamic Reconfiguration

dc.contributor.advisorMohsenin, Tinoosh
dc.contributor.authorChandrareddy, Vandana
dc.contributor.departmentComputer Science and Electrical Engineering
dc.contributor.programEngineering, Computer
dc.date.accessioned2022-09-29T15:37:44Z
dc.date.available2022-09-29T15:37:44Z
dc.date.issued2021-01-01
dc.description.abstractTime transfer is essential for global time keeping and it finds its applications in navigation, communication and tracking systems. Accurate measurement of time difference between two systems and its correction is a substantial issue while maintaining a reliable and error free communication channel. Two Way Time Transfer (TWTT) is one such method to achieve time transfer where timestamps are generated and exchanged between two sites.In this theses, we propose an entirely FPGA based transceiver architecture with an on-board digital feedback for the two-way time transfer protocol, to determine the clock offset/error between two independent systems operating at different frequencies and correct it. Digital feedback loop uses the on-board FPGA system clock generated by the MMCM primitive as its reference clock oscillator. Furthermore, a dynamic reconfiguration port(DRP) is designed to wrap the MMCM primitive which allows dynamic reconfiguration. The functionality of the design is evaluated by post implementation simulations and experiments conducted in the laboratory on the optical test setup with a 1 km fiber spool. The designed transceiver is configurable in terms of the data width, transmitter and receiver frequencies. The design can be switched to operate as master or slave and is implemented on Xilinx Virtex�-7 FPGA VC707 Evaluation Kit. The proposed model is capable of maintaining a time error in the range of 200 ns for an oscillator(running at 100 MHz) with a fractional frequency error of 4*103 (Oscilloscope measurement) while the oscillator updates are provided for every 50 us. Given the fact that all the timestamps are exchanged in a serial fashion, channel efficiency is also a metric to be considered. In this work, considering the preamble of 8 bits and timestamps of 64 bits, the channel efficiency of 89% is achieved.
dc.formatapplication:pdf
dc.genretheses
dc.identifierdoi:10.13016/m21c8q-tqpp
dc.identifier.other12435
dc.identifier.urihttp://hdl.handle.net/11603/25959
dc.languageen
dc.relation.isAvailableAtThe University of Maryland, Baltimore County (UMBC)
dc.relation.ispartofUMBC Computer Science and Electrical Engineering Department Collection
dc.relation.ispartofUMBC Theses and Dissertations Collection
dc.relation.ispartofUMBC Graduate School Collection
dc.relation.ispartofUMBC Student Collection
dc.rightsThis item may be protected under Title 17 of the U.S. Copyright Law. It is made available by UMBC for non-commercial research and education. For permission to publish or reproduce, please see http://aok.lib.umbc.edu/specoll/repro.php or contact Special Collections at speccoll(at)umbc.edu
dc.sourceOriginal File Name: Chandrareddy_umbc_0434M_12435.pdf
dc.titleFPGA based Optical Two-way Time Transfer for Clock Correction through Dynamic Reconfiguration
dc.typeText
dcterms.accessRightsAccess limited to the UMBC community. Item may possibly be obtained via Interlibrary Loan through a local library, pending author/copyright holder's permission.
dcterms.accessRightsAccess limited to the UMBC community. Item may possibly be obtained via Interlibrary Loan thorugh a local library, pending author/copyright holder's permission.

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
Chandrareddy_umbc_0434M_12435.pdf
Size:
7.29 MB
Format:
Adobe Portable Document Format