Exploring Parallel Bitonic Sort on a Migratory Thread Architecture

dc.contributor.authorVelusamy, Kaushik
dc.contributor.authorRolinger, Thomas B.
dc.contributor.authorMcMahon, Janice
dc.contributor.authorSimon, Tyler A.
dc.date.accessioned2024-02-29T16:27:47Z
dc.date.available2024-02-29T16:27:47Z
dc.date.issued2018-11-29
dc.description2018 IEEE High Performance extreme Computing Conference (HPEC), Waltham, MA, USA 25-27 September 2018
dc.description.abstractLarge scale, data-intensive applications pose challenges to systems with a traditional memory hierarchy due to their unstructured data sources and irregular memory access patterns. In response, systems that employ migratory threads have been proposed to mitigate memory access bottlenecks as well as reduce energy consumption. One such system is the Emu Chick, which migrates a small program context to the data being referenced in a memory access. Sorting an unordered list of elements is a critical kernel for countless applications, such as graph processing and tensor decomposition. As such applications can be considered highly suitable for a migratory thread architecture, it is imperative to understand the performance of sorting algorithms on these systems. In this paper, we implement parallel bitonic sort and target the Emu Chick system. We investigate the performance of an explicit comparison-based approach as well as a sorting network implementation. Furthermore, we explore two different data layouts for the parallel bitonic sorting network, namely cyclic and blocked. From the results of our performance study, we find that while thread migrations can dictate the overall performance of an application, the cost of thread creation and management can out-grow the cost of thread migration.
dc.description.sponsorshipThe authors would like to thank Dr. John Dorband, Dr. Milton Halem and Dr. TC Tuan for their continued support for this research effort. In addition, the authors thank the Center for Hybrid Multicore Productivity Research (NFS Award Number 1439633), Laboratory of Physical Sciences and Emu Technology for their support and access to their computational resources.
dc.description.urihttps://ieeexplore.ieee.org/abstract/document/8547568/
dc.format.extent7 pages
dc.genreconference papers and proceedings
dc.genrepreprints
dc.identifierdoi:10.13016/m2x4gn-nfzu
dc.identifier.citationK. Velusamy, T. B. Rolinger, J. McMahon and T. A. Simon, "Exploring Parallel Bitonic Sort on a Migratory Thread Architecture," 2018 IEEE High Performance extreme Computing Conference (HPEC), Waltham, MA, USA, 2018, pp. 1-7, doi: 10.1109/HPEC.2018.8547568.
dc.identifier.urihttps://doi.org/10.1109/HPEC.2018.8547568
dc.identifier.urihttp://hdl.handle.net/11603/31745
dc.publisherIEEE
dc.relation.isAvailableAtThe University of Maryland, Baltimore County (UMBC)
dc.relation.ispartofUMBC Computer Science and Electrical Engineering Department Collection
dc.relation.ispartofUMBC Faculty Collection
dc.relation.ispartofUMBC Student Collection
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.titleExploring Parallel Bitonic Sort on a Migratory Thread Architecture
dc.typeText

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