THE IMPACT OF DEVICE AGING ON THE RESILIENCY OF CRYPTOGRAPHIC DEVICES AGAINST PHYSICAL ATTACKS

Abstract

Cryptographic chips offer continued advances in authenticating messages and devices as well as preserving the integrity and confidentiality of sensitive information through the implementation of cryptographic algorithms in hardware. These pieces of silicon combine the benefits of cryptographic applications with the speed and power advantages of hardware implementations. Indeed, cryptographic devices are used as an essential entity in almost all systems that deal with sensitive data, e.g., banking, military, transportation, medical, internet-of-things, and cloud networks. Disruption on these devices can be forced by adversaries to uncover secret information. In fact, the probability of such devices being attacked or hacked is rapidly growing; necessitating the protection of such devices against attacks and in turn secret data leakage. One such attack that can be launched on cryptographic devices is leaking the secret key through side-channel analysis. Indeed, while operating, cryptographic devices leave traces of side-channel information such as power consumption, electromagnetic emanation, running time, and so on. This information can be utilized to conduct statistical analysis, the so-called Side-Channel Attacks (SCA), to retrieve secret information. As mentioned, although cryptographic cores have been developed to maintain security and trust, their physical implementation can be compromised by the adversaries who aim at extracting the sensitive information these chips conceal. Thereby, it is essential to assure the security of the sensitive tasks performed by these circuits and to guarantee the security of information stored within these devices. Security challenges for cryptographic devices can range from the attacks launched to directly retrieve sensitive data (e.g., Side-Channel Analysis attacks and Fault-Injection at tacks) to the attacks in which a cryptographic design is tampered via inserting hardware Trojans to ease information leakage or to cause a denial of service. Protecting cryptographic devices against all such attacks is a major security concern.Side-channel analysis attack via analyzing the device’s power consumption is one of the most popular form of attacks threatening cryptographic devices. Power analysis attacks are carried out by investigating the data being processed as well as the device’s associated power usage. In contrast to power analysis attacks, in the fault injection attacks the adversary has a more active role; injecting faults in the targeted chip to facilitate extracting sensitive data based on a comparison or correlation between the faulty and golden outputs. A wide number of countermeasures have been proposed in recent years to thwart power analysis and fault injection attacks. However, the resiliency of such countermeasures may vary in different operating conditions such as operating voltage, temperature, as well as aging-related degradation. The degradation imposed by aging is considered inevitable for electronic circuits. Therefore, it is highly important to investigate the security of devices that have been used for a while, i.e., have been aged, to ensure their security is not compromised when the devices are aged. This research focuses on the impact of device aging on the security of crypto graphic devices against side-channel analysis attacks, in particular power analysis attacks as well as the resiliency of such devices against fault injection attacks. Accordingly, we first investigated the impact of device aging on the resiliency of unprotected cryptographic devices when subject to profiling and non-profiling power analysis attacks. Then we moved one step forward to analyze the aging impact on the existing countermeasures against power analysis attacks. These countermeasures are mainly classified into two groups: hiding and masking. In our investigation, we conducted power analysis attacks on hiding-protected devices when new and when aged. In particular, we target Sense Amplifier Based Logic (SABL) and Wave Dynamic Differential Logic (WDDL) circuits as the two main existing hiding countermeasures. We showed that, the success rate of the power analysis attacks increases in both SABL- and WDDL-protected circuits over time, i.e., their security diminishes over time. To address the problem, we propose an aging-resilient variation of the SABL circuit to ensure long-lasting security. We also investigated the impact of device aging on several state-of-the-art masking countermeasures tailored to protect against power analysis attacks. The results showed that the protection offered by the state-of-the-art masked devices fluctuates with aging. This may potentially expose the device to vulnerabilities as it ages. Finally, we validated our findings on real silicon, specifically on FPGA. In order to protect cryptographic devices against fault injection attacks, we developed a digital-sensor based failure-detection framework, devised an efficient characterization methodology for the considered sensor, and proposed an aging aware dimensioning algorithm to optimize the sensor hardware based on the whole range of operating conditions. We showed the efficiency of the proposed framework in detecting fault attacks induced by change of temperature, voltage, and clock frequency. These findings were also evaluated using platforms. In sum, our solutions provide long lasting security for cryptographic devices against physical attacks and thus highly benefits the industry and government sectors.