Power Supply Analysis for Device Verification
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Author/Creator ORCID
Date
2020-01-20
Type of Work
Department
Computer Science and Electrical Engineering
Program
Engineering, Electrical
Citation of Original Publication
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Distribution Rights granted to UMBC by the author.
This item may be protected under Title 17 of the U.S. Copyright Law. It is made available by UMBC for non-commercial research and education. For permission to publish or reproduce, please see http://aok.lib.umbc.edu/specoll/repro.php or contact Special Collections at speccoll(at)umbc.edu
This item may be protected under Title 17 of the U.S. Copyright Law. It is made available by UMBC for non-commercial research and education. For permission to publish or reproduce, please see http://aok.lib.umbc.edu/specoll/repro.php or contact Special Collections at speccoll(at)umbc.edu
Subjects
Abstract
With the global spanning of integrated circuit (IC) and electronic device supply chains, the ability of an untrusted entity to alter an IC or device while it is in the supply chain increases. There is also an increased ability to intercept and alter or introduce an altered version of a product with a global supply chain. This work seeks to verify devices through the use of power supply analysis on three focus areas: Solid-State Drives (SSDs) operation verification, IC identification, and Field Programmable Gate Array (FPGA) bitstream verification. The first focus area is using power supply analysis on an SSD to ensure that the device is operating properly. This work started with identifying trim operation signatures and then using machine learning to reach near 100 percent accuracy at identifying the operation. Follow on applications include read and write classification, operating system identification, and malware detection on SSDs. The second focus area is using current analysis to identify alterations in an IC even if the IC is functionally equivalent. This work is done through simulation and captures process variation, noise, and aging at multiple different temperatures all with greater than an F1 score of 0.90 given at least 2.5 percent of the circuit had been altered. Additionally, various machine learning techniques are applied to increase performance and lower the detection floor to than 2 percent of the circuit and in most cases 1 percent of the circuit. The application for this focus area is the ability to identify ICs to ensure that the desired IC is used in a final product and make it more difficult for piraters. The final focus area is using current analysis to verify a bitstream that is on an FPGA. Given a set of known bitstreams, the presented method results in a minimum F1 score of 0.8832 at determining if a bitstream is the desired version. This is accomplished by using both support vector machines and neural networks to determine changes in the FPGA fabric. Altered circuits ranged from 0.087 to 20.05 percent change in the underlying fabric while maintaining a functionally equivalent implementation. The application of this ensures that the correct bitstream is running on an FPGA. The three focus areas independently help to verify a device but can be combined to more completely verify a device. Monitoring its operations on the device level as well as the chip level, whether the chip is an Application-Specific Integrated Circuit (ASIC) or an FPGA, can make pirating cost-prohibitive.