Exploring High-Level Neural Networks Architectures for Efficient Spiking Neural Networks Implementation

Abstract

The microprocessor industry faces several challenges: total power consumption, processor speed, and increasing chip cost. It is visible that the processor speed in the last decade has not improved and saturated around 2 GHz to 5 GHz. Researchers believe that brain-inspired computing has great potential to resolve these problems. The spiking neural network (SNN) exhibits excellent power performance compared to the conventional design. However, we identified several key challenges to implementing large-scale neural networks (NNs) on silicon, such as nonexistent automated tools and requirements of many-domain expertise, and existing algorithms can not partition and place large-scale SNN computation efficiently on the hardware. In this research, we propose to develop an automated tool flow that can convert any NN to an SNN. In this process, we will develop a novel graph-partitioning algorithm and place SNN on a network-on-chip (NoC) to enable future energy-efficient and high-performance computing.