A Hardware Accelerator for Language Guided Reinforcement Learning
| dc.contributor.author | Shiri, Aidin | |
| dc.contributor.author | Mazumder, Arnab Neelim | |
| dc.contributor.author | Prakash, Bharat | |
| dc.contributor.author | Homayoun, Houman | |
| dc.contributor.author | Waytowich, Nicholas R. | |
| dc.contributor.author | Mohsenin, Tinoosh | |
| dc.date.accessioned | 2021-03-26T16:31:32Z | |
| dc.date.available | 2021-03-26T16:31:32Z | |
| dc.date.issued | 2021-03-02 | |
| dc.description.abstract | Reinforcement learning (RL) has shown great performance in solving sequential decision-making problems. This paper proposes a framework to train RL agents conditioned on constraints that are in the form of structured language to improve training efficiency. We implemented an energy-efficient hardware accelerator to receive both images and text inputs that allows RL agents understand human language and act in real-world environments. A scalable and parallel hardware with different number of processing elements is implemented on both FPGA and ASIC that provides a balance between power consumption and performance. The post-layout ASIC design consumes 9.2 mW while providing 361 fps throughput. | en_US |
| dc.description.sponsorship | This project was sponsored by the U.S. Army Research Laboratory under Cooperative Agreement Number W911NF10-2-0022. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein | en_US |
| dc.description.uri | https://ieeexplore.ieee.org/document/9367213/ | en_US |
| dc.format.extent | 6 pages | en_US |
| dc.genre | journal articles | en_US |
| dc.identifier | doi:10.13016/m23do0-qgag | |
| dc.identifier.citation | A. Shiri, A. N. Mazumder, B. Prakash, H. Homayoun, N. R. Waytowich and T. Mohsenin, "A Hardware Accelerator for Language Guided Reinforcement Learning," in IEEE Design & Test, doi: 10.1109/MDAT.2021.3063363. | en_US |
| dc.identifier.uri | https://doi.org/10.1109/MDAT.2021.3063363 | |
| dc.identifier.uri | http://hdl.handle.net/11603/21225 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | IEEE | en_US |
| dc.relation.isAvailableAt | The University of Maryland, Baltimore County (UMBC) | |
| dc.relation.ispartof | UMBC Computer Science and Electrical Engineering Department Collection | |
| dc.relation.ispartof | UMBC Faculty Collection | |
| dc.relation.ispartof | UMBC Student Collection | |
| dc.rights | This item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author. | |
| dc.rights | Public Domain Mark 1.0 | * |
| dc.rights | This work was written as part of one of the author's official duties as an Employee of the United States Government and is therefore a work of the United States Government. In accordance with 17 U.S.C. 105, no copyright protection is available for such works under U.S. Law | |
| dc.rights.uri | http://creativecommons.org/publicdomain/mark/1.0/ | * |
| dc.title | A Hardware Accelerator for Language Guided Reinforcement Learning | en_US |
| dc.type | Text | en_US |