XMT-GPU: A PRAM Architecture for Graphics Computation
| dc.contributor.author | DuBois, Thomas M. | |
| dc.contributor.author | Lee, Bryant | |
| dc.contributor.author | Wang, Yi | |
| dc.contributor.author | Olano, Marc | |
| dc.contributor.author | Vishkin, Uzi | |
| dc.date.accessioned | 2026-02-03T18:14:49Z | |
| dc.date.issued | 2008-09 | |
| dc.description | 37th International Conference on Parallel Processing, September 9 -12, 2008, Portland, OR, USA | |
| dc.description.abstract | The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing these processors with a fully general-purpose parallel processor, without the fixed-function graphics hardware legacy of current graphics processing units (GPUs). The representative general-purpose processor we test against is XMT (for eXplicit Multi-Threading), a PRAM-like single-chip parallel architecture. Performance is compared for two characteristic shaders running in a fragment-limited GPU benchmark harness and on a cycle-accurate XMT simulator. The general-purpose processor is found to be significantly faster at a compute-only shader, but slower on a memory bound texture shader. Finally we analyze the design tradeoffs that would allow combining the best of both worlds: (i) a competitive XMT texture shader, with (ii) a general-purpose easy-to-program XMT many-core approach that scales up or down to the amount of parallelism provided by the application and is even compatible with serial code. | |
| dc.description.sponsorship | Supported in part by NSF ITR Award CNS-0426683, NSF Award CNS-0626964, NSF grant CCF-0325393, and NSF STTR Award IIP0339489. | |
| dc.description.uri | https://ieeexplore.ieee.org/abstract/document/4625870 | |
| dc.format.extent | 9 pages | |
| dc.genre | conference papers and proceedings | |
| dc.genre | preprints | |
| dc.identifier | doi:10.13016/m26wsy-og6q | |
| dc.identifier.citation | DuBois, Thomas M., Bryant Lee, Yi Wang, Marc Olano, and Uzi Vishkin. “XMT-GPU: A PRAM Architecture for Graphics Computation.” 2008 37th International Conference on Parallel Processing, September 2008, 364–72. https://doi.org/10.1109/ICPP.2008.35. | |
| dc.identifier.uri | https://doi.org/10.1109/ICPP.2008.35 | |
| dc.identifier.uri | http://hdl.handle.net/11603/41666 | |
| dc.language.iso | en | |
| dc.publisher | IEEE | |
| dc.relation.isAvailableAt | The University of Maryland, Baltimore County (UMBC) | |
| dc.relation.ispartof | UMBC College of Engineering and Information Technology Dean's Office | |
| dc.relation.ispartof | UMBC Faculty Collection | |
| dc.relation.ispartof | UMBC Computer Science and Electrical Engineering Department | |
| dc.rights | © 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |
| dc.subject | general-purpose | |
| dc.subject | UMBC Ebiquity Research Group | |
| dc.subject | Computer architecture | |
| dc.subject | pram-on-chip | |
| dc.subject | Hardware | |
| dc.subject | Pipelines | |
| dc.subject | XMT | |
| dc.subject | GPU | |
| dc.subject | Program processors | |
| dc.subject | Graphics | |
| dc.subject | Phase change random access memory | |
| dc.subject | PRAM | |
| dc.subject | Computational modeling | |
| dc.title | XMT-GPU: A PRAM Architecture for Graphics Computation | |
| dc.type | Text | |
| dcterms.creator | https://orcid.org/0000-0003-4209-6103 |
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