Feasibility Prediction for Rapid IC Design Space Exploration
| dc.contributor.author | Islam, Riadul | |
| dc.date.accessioned | 2022-05-31T13:27:42Z | |
| dc.date.available | 2022-05-31T13:27:42Z | |
| dc.date.issued | 2020-04-06 | |
| dc.description.abstract | The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty. | en_US |
| dc.description.sponsorship | We acknowledge M. K. Devnath and M. Galib’s contributions to data analysis and figure generations. This research was funded in part by UMBC start up grant, Rezonent Inc. award number: CORP-0061, National Science Foundation (NSF) award number: 2138253, and Office of Naval Research (ONR) award number: N00014-21-1-2531. | en_US |
| dc.description.uri | https://www.mdpi.com/2079-9292/11/7/1161 | en_US |
| dc.format.extent | 11 pages | en_US |
| dc.genre | journal articles | en_US |
| dc.identifier | doi:10.13016/m2kafz-nkfi | |
| dc.identifier.citation | Islam, Riadul. 2022. "Feasibility Prediction for Rapid IC Design Space Exploration" Electronics 11, no. 7: 1161. https://doi.org/10.3390/electronics11071161 | en_US |
| dc.identifier.uri | https://doi.org/10.3390/electronics11071161 | |
| dc.identifier.uri | http://hdl.handle.net/11603/24759 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | MDPI | en_US |
| dc.relation.isAvailableAt | The University of Maryland, Baltimore County (UMBC) | |
| dc.relation.ispartof | UMBC Computer Science and Electrical Engineering Department Collection | |
| dc.relation.ispartof | UMBC Faculty Collection | |
| dc.rights | This item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author. | en_US |
| dc.rights | Attribution 4.0 International (CC BY 4.0) | * |
| dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | * |
| dc.title | Feasibility Prediction for Rapid IC Design Space Exploration | en_US |
| dc.type | Text | en_US |
| dcterms.creator | https://orcid.org/0000-0002-4649-3467 | en_US |