Browsing by Author "Bezzam, Ignatius"
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Item Design Automation of Series Resonance Clocking in 14-nm FinFETs(Springer, 2021) Challagundla, Dhandeep; Bezzam, Ignatius; Islam, RiadulPower-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor-capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to conventional primary-secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% powerItem Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks(IEEE, 2022-11-11) Challagundla, Dhandeep; Galib, Md Mehedi Hassan; Bezzam, Ignatius; Islam, RiadulAs the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1--5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.Item Resonant Energy Recycling SRAM Architecture(IEEE) Islam, Riadul; Saha, Biprangshu; Bezzam, IgnatiusAlthough we may be at the end of Moore’s law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.