Design Automation of Series Resonance Clocking in 14-nm FinFETs
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Author/Creator
Author/Creator ORCID
Date
2021
Type of Work
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Citation of Original Publication
Challagundla, Dhandeep, Ignatius Bezzam and Riadul Islam. "Design Automation of Series Resonance Clocking in 14-nm FinFETs" Springer Circuits, Systems, and Signal Processing (CSSP) 2021.
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This version of the article has been accepted for publication, after peer review (when applicable) and is subject to Springer Nature’s AM terms of use, but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: https://doi.org/10.1007/s00034-023-02458-4.
Subjects
Abstract
Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in
the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting
in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy
using series inductor-capacitor (LC) resonance. Moreover, this work
also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance,
the switching power dissipated is recycled back. The inductor tuning
technique aids in reducing the skew, increasing the robustness of the
clock networks. This new resonant clocking architecture saves over 43%
power and 90% reduced skew in clock tree networks and saves 44%
power and 90% reduced skew in clock mesh networks, clocking a range
of 1-5 GHz frequency, compared to conventional primary-secondary
flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power