Design Automation of Series Resonance Clocking in 14-nm FinFETs
dc.contributor.author | Challagundla, Dhandeep | |
dc.contributor.author | Bezzam, Ignatius | |
dc.contributor.author | Islam, Riadul | |
dc.date.accessioned | 2023-08-08T22:42:32Z | |
dc.date.available | 2023-08-08T22:42:32Z | |
dc.date.issued | 2023-08-01 | |
dc.description.abstract | Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor-capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to conventional primary-secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power | en_US |
dc.description.sponsorship | This work was supported in part by Rezonent Inc. under Grant CORP-0061, National Science Foundation (NSF) award number: 2138253, and UMBC Startup grant. The authors also acknowledge M. Galib from UMBC for providing layouts data used in the analysis. | en_US |
dc.description.uri | https://link.springer.com/article/10.1007/s00034-023-02458-4 | en_US |
dc.format.extent | 32 pages | en_US |
dc.genre | journal articles | en_US |
dc.genre | postprints | en_US |
dc.identifier | doi:10.13016/m2vphq-y7w7 | |
dc.identifier.citation | Challagundla, Dhandeep, Ignatius Bezzam and Riadul Islam. "Design Automation of Series Resonance Clocking in 14-nm FinFETs" Springer Circuits, Systems, and Signal Processing (CSSP) 2021. | en_US |
dc.identifier.uri | https://doi.org/10.1007/s00034-023-02458-4 | |
dc.identifier.uri | http://hdl.handle.net/11603/29127 | |
dc.language.iso | en_US | en_US |
dc.publisher | Springer | en_US |
dc.relation.isAvailableAt | The University of Maryland, Baltimore County (UMBC) | |
dc.relation.ispartof | UMBC Computer Science and Electrical Engineering Department Collection | |
dc.relation.ispartof | UMBC Faculty Collection | |
dc.relation.ispartof | UMBC Student Collection | |
dc.rights | This version of the article has been accepted for publication, after peer review (when applicable) and is subject to Springer Nature’s AM terms of use, but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: https://doi.org/10.1007/s00034-023-02458-4. | en_US |
dc.title | Design Automation of Series Resonance Clocking in 14-nm FinFETs | en_US |
dc.type | Text | en_US |
dcterms.creator | https://orcid.org/0000-0002-4649-3467 | en_US |