Feasibility Prediction for Rapid IC Design Space Exploration

Thumbnail Image

Files

electronics-11-01161.pdf (424.07 KB)

Links to Files

https://www.mdpi.com/2079-9292/11/7/1161

Permanent Link

https://doi.org/10.3390/electronics11071161
 http://hdl.handle.net/11603/24759

Collections

UMBC Computer Science and Electrical Engineering Department
UMBC Faculty Collection

Author/Creator

Author/Creator ORCID

https://orcid.org/0000-0002-4649-3467

Date

2020-04-06

Type of Work

journal articles
Text

Department

Program

Citation of Original Publication

Islam, Riadul. 2022. "Feasibility Prediction for Rapid IC Design Space Exploration" Electronics 11, no. 7: 1161. https://doi.org/10.3390/electronics11071161

Rights

This item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author.
Attribution 4.0 International (CC BY 4.0)

Subjects

Abstract

The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty.