A Fast Method to Fine-Tune Neural Networks for the Least Energy Consumption on FPGAs
| dc.contributor.author | Hosseini, Morteza | |
| dc.contributor.author | Ebrahimabadi, Mohammad | |
| dc.contributor.author | Mazumder, Arnab Neelim | |
| dc.contributor.author | Homayoun, Houman | |
| dc.contributor.author | Mohsenin, Tinoosh | |
| dc.date.accessioned | 2021-07-26T16:32:06Z | |
| dc.date.available | 2021-07-26T16:32:06Z | |
| dc.date.issued | 2021 | |
| dc.description | HAET workshop of ICLR 2021 | en_US |
| dc.description.abstract | Because of their simple hardware requirements, low bitwidth neural networks (NNs) have gained significant attention over the recent years, and have been extensively employed in electronic devices that seek efficiency and performance. Research has shown that scaled-up low bitwidth NNs can have accuracy levels on par with their full-precision counterparts. As a result, there seems to be a tradeoff between quantization (q) and scaling (s) of NNs to maintain the accuracy. In this paper, we propose QS-NAS which is a systematic approach to explore the best quantization and scaling factors for a NN architecture that satisfies a targeted accuracy level and results in the least energy consumption per inference when deployed to a hardware–FPGA in this work. Compared to the literature using the same VGG-like NN with different q and s over the same datasets, our selected optimal NNs deployed to a low-cost tiny Xilinx FPGA from the ZedBoard resulted in accuracy levels higher or on par with those of the related work, while giving the least power dissipation and the highest inference/Joule. | en_US |
| dc.description.uri | https://eehpc.csee.umbc.edu/publications/pdf/2021/A_fast_method.pdf | en_US |
| dc.format.extent | 5 pages | en_US |
| dc.genre | conference papers and proceedings | en_US |
| dc.identifier | doi:10.13016/m2m8bc-5lxc | |
| dc.identifier.citation | Hosseini, Morteza et al.; A Fast Method to Fine-Tune Neural Networks for the Least Energy Consumption on FPGAs; HAET workshop of ICLR 2021; https://eehpc.csee.umbc.edu/publications/pdf/2021/A_fast_method.pdf | en_US |
| dc.identifier.uri | http://hdl.handle.net/11603/22103 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | UMBC Energy Efficient High Performance Computing Lab | en_US |
| dc.relation.isAvailableAt | The University of Maryland, Baltimore County (UMBC) | |
| dc.relation.ispartof | UMBC Computer Science and Electrical Engineering Department Collection | |
| dc.relation.ispartof | UMBC Faculty Collection | |
| dc.relation.ispartof | UMBC Student Collection | |
| dc.rights | This item is likely protected under Title 17 of the U.S. Copyright Law. Unless on a Creative Commons license, for uses protected by Copyright Law, contact the copyright holder or the author. | |
| dc.title | A Fast Method to Fine-Tune Neural Networks for the Least Energy Consumption on FPGAs | en_US |
| dc.type | Text | en_US |